From ab5914b269cfee8c73de8403253066487fd128e5 Mon Sep 17 00:00:00 2001 From: Ivsucram Date: Sun, 1 Aug 2021 12:49:28 +0800 Subject: [PATCH] Simple modulo optimization As we are using a base 2 for our RHS modulo operator, we changed that for a bitwise and operator, which is faster. In other words, if the RHS of the modulo operator (i.e. LHS % RHS) is a base 2, we can write "LHS & (RHS -1)", which will yield the same results but with a faster processing time. --- src/chip_8/cpu/cpu.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/chip_8/cpu/cpu.rs b/src/chip_8/cpu/cpu.rs index 5eb8bdf..a20583f 100644 --- a/src/chip_8/cpu/cpu.rs +++ b/src/chip_8/cpu/cpu.rs @@ -345,8 +345,8 @@ fn op_cxnn(cpu: &mut CPU) { fn op_dxyn(cpu: &mut CPU) { let mut vf: bool = false; let value = cpu.op.n as usize; - let ori_x = cpu.regs.get(cpu.op.x) as usize % WIDTH; - let ori_y = cpu.regs.get(cpu.op.y) as usize % HEIGHT; + let ori_x = cpu.regs.get(cpu.op.x) as usize & (WIDTH - 1); //% WIDTH; + let ori_y = cpu.regs.get(cpu.op.y) as usize & (HEIGHT -1); //% HEIGHT; for row in 0..value { let y = ori_y + row;